This course provides an in-depth exploration of the principles, techniques, and applications of three-dimensional integrated circuit (3D IC) packaging. 3D IC packaging is a cutting-edge technology that enables the stacking of multiple integrated circuits (ICs) within a single package, offering numerous advantages in terms of performance, power efficiency, and form factor.
The course begins with an introduction to the fundamentals of IC packaging, including various packaging technologies and their evolution. It then delves into the concepts and challenges associated with 3D IC packaging. Students will gain a comprehensive understanding of the design considerations, fabrication processes, and assembly techniques employed in 3D IC packaging. The course also covers topics like EMIR and has comprehensive physical verification in the areas of chip stacking.
Some familiarity with material science principles and a fundamental knowledge of semiconductor manufacturing processes.
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience.
To see all meeting dates, click "Full Schedule" below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Recommended Text(s):
3D IC Stacking Technology; Wu, Kumar and Ramaswami; McGraw Hill Professional, 2011. ISBN: 9780071741965
