Learn to design, code, and test digital circuits using Verilog in hands-on logic design projects.
This course is a practical introduction to digital logic design using Verilog as a hardware description language. Students learn Verilog constructs and hardware modeling techniques using numerous examples of coding and modeling digital circuits and sub-blocks. Verilog remains the legacy hardware description language for digital designs in the industry.
The course starts with the basic concepts of hardware description, then goes into the key Verilog language elements and data types. Students tackle key challenges and learn structural, dataflow and behavioral modeling in Verilog, including common constructs, considerations and coding examples. Instruction in the coding and testing of digital logic includes examples of combinational circuits (gates, mux/demux, encoders/decoders, and general Boolean expression), sequential circuits (various latches, flip-flops, shift registers, counters, RAMs and ROMs), and complex logic (flavors of ALU and FSM).
At the completion of the course, students are able to understand and implement Verilog modeling of basic digital logic. Ultimately, students write and simulate approximately 3000 lines of Verilog code. The synthesis and simulation of the test examples is done using freely downloadable tools with instructor guidance.
Knowledge of basic logic design and familiarity with a high-level programming language (e.g., C) and use of a text editor.
09/10/2025: Schedule change. Please review full schedule for details.
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.
No meeting on November 27, 2025. To see all meeting dates, click "Full Schedule" below.
Electronic Course Materials: You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Tool: Verilog Simulator, and Synthesis tools.
Please see Modules in Canvas on how to access the tools.
