Course Description

Universal Verification Methodology (UVM) is the industry standard for functional verification methodology developed by key EDA vendors and industry leaders. It uses a SystemVerilog-based, OOP-centric approach to improve interoperability and code reusability. In this course, you will use the OOP testbench knowledge learned earlier to create a full-fledged, flexible verification environment for solving today¡¯s increasingly complex functional verification challenges. You will also gain real-world, hands-on experience developing an industrial-strength UVM-based testbench that is layered, interoperable, constrained-random, and coverage-driven.

The course introduces the UVM architecture; its core set of base-classes and utility methods, and associated factory automation techniques. This framework forms the basic building blocks that facilitate the development of layered, modular, scalable, and reusable verification environments in SystemVerilog. You will be immersed in the practical application and deployment of UVM base-classes, understand their role in the verification environment to reduce design time and risks, as well as increasing quality and efficiency. The main base-classes covered are the UVM test classes, sequence classes, component classes, messaging and reporting mechanism, factory, configuration database, transaction-level modeling (TLM), scoreboarding, coverage and phasing mechanism. You will learn the power of UVM for successfully designing complex constraint-random coverage driven verification projects.

Concepts introduced in class are reinforced in the lab. In addition to in-class hands-on labs and weekly take-home assignments, you¡¯ll work on a project to build an advanced UVM verification environment for a selected application with transaction-level and layered architecture. You will form a project team, create a test plan, develop a UVM-based verification environment, perform functional coverage, and submit a complete project report.