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Semiconductor Design and Innovation Workshop Series

This half-day workshop introduces you to a commercial RISC-V system, covering theory, architecture, and technical aspects of the RISC-V ISA. As an open-source, extensible ISA, RISC-V is shaping the future of computing.

Instructor Abhay Singh, a Silicon Operations and Partnerships manager at Google, will guide you through the material and share its real-world implications.

This event is taught in person at the UC Santa Cruz Silicon Valley Campus in Santa Clara and online. Students who attend in person are required to bring laptops for class exercises.

Learning Outcomes

• Describe and discuss the architecture of RISC-V processors, their fundamental components, and how they compare to other instruction set architectures in modern computing systems.
   
• Identify critical hardware and software components within a RISC-V system-on-chip design, including memory interfaces, peripherals, and the toolchain required for development.
   
• Demonstrate an ability to properly and effectively design, implement, and debug custom RISC-V-based systems and understanding of the RISC-V industry trend.

Topics

• The nature, history, and ongoing practices of RISC-V as a technology, and about RISC-V international organization
• RISC-V Architecture and Components
• Analyzing and modifying the RISC-V-core and memory hierarchy

Organizer

This event is organized by the Silicon Chip Design and Semiconductor Engineering certificate program at ºÚÁϲ»´òìÈ Silicon Valley Extension.